Digital circuit components may be connected together in synchronous circuits whereby processing is performed in reference to one or more clock signals. In many applications, only one clock signal is used as a reference for processing because of the system's characteristics and/or because of cost considerations. Often, some of the integrated circuits of the systems cannot possibly operate at their full capacity when only one clock is used. This is especially true in light of recent strides in IC fabrication which have produced logic gates with propagation delay times much smaller than the clock cycle of the system clock. As such, the logic gate is mostly idle between processing steps as it awaits the next clock cycle of the system clock. Unless the system is redesigned to operate in an asynchronous manner, its efficiency may only be increased by increasing the speed of the system clock.
In a fully optimized system, several different avenues are available for increasing the system clock frequency, but most require complicated circuit designs. However, one avenue, which utilizes one-shot circuits, is less complex than most of the other avenues and requires the least amount of surface space.
The one-shot circuit is a mono-stable circuit which has one stable state and one quasi-stable state. In other words, a one-shot circuit, after being placed in its stable state will remain in that state indefinitely. However, if the one-shot circuit is placed in its quasi-stable state, it will remain in the quasi-stable state for only a fixed time before reverting to its stable state.
The prior art has largely avoided the use of one-shot circuits for optimizing system clocks because of its sensitivity to changes in the environment and process. Such short comings render one-shot circuits difficult to cascade. The one-shot signal output is further difficult to delay using a series of daisy-chained inverters as the resulting output pulse width is non-uniform. Further, the pulse amplitude often effectively disappears after two or three delay units of the daisy-chained inverters.
It is therefore an object of the present invention to provide a multi-pulse signal generator whose individual stages comprise cascaded one-shot circuits and which is capable of producing a one-shot pulse delayed from the trigger signal by a relatively long delay period.